arch: arm64: entry: fix trampoline for unhandled exceptions
(cherry pick from commit 9ee88e8b5e4e04a4619a1a9fa7d5078eb9430c6c)
These commits set up a trampoline in the AArch64 kernel entry points, to
optimize for Denver's branch predictor:
18cfa15 arm64: optimize el0_sync branch prediction
153bd39 arm64: optimize exception vector branch prediction
However these patches miss setting up the trampoline for the el0_inv
fallback case, which can happen e.g. when handling a PC alignment
exception caused by a compat task. If the entry routines branch to
el0_inv without going through the trampoline, the kernel will handle the
exception but then panic when returning to userspace.
Bug: 24817444
Change-Id: I11045df3e35b8ddeb1133f73e3e41cef933e841c
Signed-off-by: Greg Hackmann <ghackmann@google.com>
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index cd98b3f..610c13c 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -380,7 +380,8 @@
adr x26, el0_dbg
cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
b.ge el0_sync_tramp
- b el0_inv
+ adr x26, el0_inv
+ b el0_sync_tramp
#ifdef CONFIG_COMPAT
.align 6
@@ -428,7 +429,7 @@
adr x26, el0_dbg
cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
b.ge el0_sync_tramp
- b el0_inv
+ adr x26, el0_inv
el0_sync_tramp:
blr x26
/* Fall through */